Satya Se

 I strongly suspect the chips used in the weighing machines are time closed only in the 'max' corner...:( Waking up early seems to have lot of time...useful skew..helps in meeting timing... - Satya se PD is immune to intelligence...artificial or otherwise... "how many click cycles one can hold the tummy tucked in" is the new hold check... Bhagwaan ke ghar mein der se setup violation hosaktha hai par andher se kabhi hold violation nahi… OnlyvTendulkar made more runs than a PD Engineer one should always appreciate oneself...do not depend on others... The new hold check is “for how long a Banarasi can hold the paan without speaking or spitting”…haven’t seen a violation yet

  Silicon Ensemble, Astro, Apollo, MilkyWay, virtuoso, Dracula, assura, calibre, physically knowledgeable synthesis, physical compiler, design compiler, rtl compiler, talus, Celtic, voltagestorm, hspice, eye see compiler and brother, innovus, red hot hawk, fusion compiler, genius without an eye, prime time, eye sea v, tweaker, formality, yell-e-see… The tools, the weapons we use In the war against the rakshasa violations that spring up on the way to the sign off and attain moksha  Let us acknowledge their everyday support as part of the Ayudha puja on this auspicious day

 Invoke the stove and fire the job with the lighter. Take a pan or bowl with the right die size estimate and initiate floorplan.  The key is the tiragamatha or tadka like library and tech files. Pour some ghee, add all the sanaga, minapa, avalu, mentulu in it. Allow them to fry, read libs. these r all like the tech files, layer files, track files, parasitic tech files.  Add ground nuts, cashews, karepaku, ginger like the blockages, bounds, placement constraints. Add water and let it boil…link, elaborate. Add the salt and turmeric. These are like clock constraints and upf. Don’t add it more as it will be too much for the tool to optimize. Add just enough for best optimisation. It is very important to read the correct rtl. Suji/Upma ravva and idly ravva looks the same. If u use wrong one, lec will fail. Read rtl, while stirring, let it compile.  Timing is important. Stir it just fast enough so the ravva doesn’t accumulate and gets mixed properly. If u add more ravva, i...

  Timing Signoff corners PD engineer after a tapeout. Coaster rollers are daily stuff; no big deal Functional ECO waking up a closed partition VLSI se door rehna. PD se to double spacing hi rakhna When you are an STA engineer and can’t do away with timing and clock

 The output of this deadly virus causes lock downs Solution below cOR + reverse of aNOR = cORONa

  once upon a time, there used to be a small village by name visiopur in a schematic district of frontend desh. People lived there happily with good amount of logic, small gates, well connected and clock reset coming on time. The village had a cpu house owned by Thakur RTL Kapoor who used to take care of all with his fabric. This Thakur worked in the security and once caught and threw a bug which a great robber Gabbar Illogic Singh created. Since then Gabbar was very angry on the Thakur. Once when the Thakur went abroad for a tech conference, the Gabbar came to the visio and disconnected all nets and pins in the cpu house. Even small logic gates were not spared. every single pin was floating. When Thakur came and say this, he went to kill the illogic but without proper power grid. Gabbar caught the Thakur and mercilessly cut his clock and reset arms. For many years the visio went totally illogical. Meanwhile Thakur rtl kappor found two coding schemes in the open source. Jai vhdl an...

 Arjuna, the PD Engineer looks at all the logic that synthesized and waiting outside the die to enter the battlefield of the floorplan. He takes a look at the army and all those IOs, Hard macros, memories, module wise standard cells lined up. Raring to get into the floorplan and get placed and routed. They all are same logic cells…same technology, process…nand, and, memory bits, flops, good old analog cells, young latches…all related to each other…raring to optimize out…agree some are having more delay and behave in adharma but every cell has its constraints and not every path meets the timing…I am ok if we don’t meet the timing and drcs…let there be bugs…but I don’t want to optimize my own logic…I cant just place them and route their nets…it will only lead to lot of congestion and leakage…I cant fire my clock and trigger the flops and the logic between them…I spent so much time, effort and faced jitters, uncertainties, variations and all to acquire high speed uclks, dclks only to ...