Joyous Pmos switching

 

Not so many years back, the semiconductor industry was baffled with one issue…across companies and projects, things started behaving rather vaguely…suddenly simulations were failing, timing, physical verification, atpg everything is failing badly…lot of debug went in but in vain…surprisingly within 1-2 days all the results came back to normal…without any change…the industry came together and formed a Mission March 7 to figure out whats happening…Captain Jack sparrow, one of the team members did an extensive study and observed that the clock on period has increased quite a bit; the clocks are switching much faster…the pmos power consumption has increased considerably due to high switching and more so because as if all the pmos in the design are switching simultaneously as if in a celebration…memory reads are much faster…the alternate drive cells are all increased in width and driving much faster…the odd metals m1-m3-m7…are all increased in width and reduced spacing…theres a lot of crosstalk among them causing big timing violations and congestion…the congestion map shows as if all the vertical metals are in a party get together…and then he figured out…the design is by design symmetric…the nmos, pmos, the duty cycle…everything…but come March 7^th the symmetry is gone…there is a joy…joy of Women’s day coming the next day…the high switching, the faster clocks everything seems to be a celebration of the upcoming Women’s day…the committee finally recommended a holiday on the 7^th eve to 9^th March for all the VLSI work…Happy International Women's day :)