From dear kanth 🙂
The Physical Design Geetha
Arjuna, the PD Engineer looks at all the logic that synthesized and waiting outside the die to enter the battlefield of the floorplan. He takes a look at the army and all those IOs, Hard macros, memories, module wise standard cells lined up. Raring to get into the floorplan and get placed and routed. They all are same logic cells…same technology, process…nand, and, memory bits, flops, good old analog cells, young latches…all related to each other…raring to optimize out…agree some are having more delay and behave in adharma but every cell has its constraints and not every path meets the timing…I am ok if we don’t meet the timing and drcs…let there be bugs…but I don’t want to optimize my own logic…I cant just place them and route their nets…it will only lead to lot of congestion and leakage…I cant fire my clock and trigger the flops and the logic between them…I spent so much time, effort and faced jitters, uncertainties, variations and all to acquire high speed uclks, dclks only to ...
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